View SMJ27C256-17JM_9097313.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? organized 32,768 x 8 ? single +5v 10% power supply ? pin-compatible with existing 256k roms and eproms ? all inputs/outputs fully ttl compatible ? power-saving cmos technology ? very high-speed snap! pulse programming ? 3-state output buffers ? 400-mv dc assured noise immunity with standarad ttl loads ? latchup immunity of 250 ma on all input and output pins ? low power dissipation (cmos input levels) p active - 165mw worst case p standby - 1.7mw worst case (cmos-input levels) options marking ? timing 150ns access -15 170ns access -17 200ns access -20 250ns access -25 300ns access -30 ? package(s) ceramic dip (600mils) j no. 110 ? operating temperature ranges military (-55 o c to +125 o c) m pin assignment (top view) available as military specifications ? smd 5962-86063 ? mil-std-883 32-pin dip (j) (600 mil) 256k uveprom uv erasable programmable read-only memory for more products and information please visit our web site at www.austinsemiconductor.com general description the smj27c256 series is a set of 262,144 bit, ultraviolet- light erasable, electrically programmable read-only memories. these devices are fabricated using power-saving cmos technology for high speed and simple interface with mos and bipolar circuits. all inputs (including program data inputs) can be driven by series 54 ttl circuits without the use of external pullup resistors. each output can drive one series 54 ttl circuit without external resistors. the data outputs are 3-state for connecting multiple devices to a common bus. the smj27c256 is pin-compatible with 28-pin 256k roms and eproms. it is offered in a 600mil dual-in-line ceramic pagackage (j suffix) rated for operation from -55c to 125c. because this eprom operates from a single 5v supply (in the read mode), it is ideal for use in microprocessor-based systems. one other supply (13v) is needed for programming. all programming signals are ttl level. this device is programmable by the snap! pulse programming algorithm. the snap! pulse programming algorithm uses a v pp of 13v and a v cc of 6.5v for a nominal programming time of four seconds. for programming outside the system, existing eprom programmers can be used. locations can be programmed singly, in blocks, or at random. pin name function a0 - a14 address inputs da0-dq7 inputs (programming)/outputs e\ chip enable/power down g\ output enable gnd ground v cc 5v supply v pp 13v programming power supply 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v pp a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc a14 a13 a8 a9 a11 g\ a10 e\ dq7 dq6 dq5 dq4 dq3
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram* operation the seven modes of operation for the smj27c256 are listed in table 1. the read mode requires a single 5v supply. all inputs are ttl level except for v pp during programming (13v for snap! pulse), and (12v) on a9 for signature mode. table 1. operation modes * x can be v il or v ih . * this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. a0 a1 a2 a3 a4 a5 dq0 a6 dq1 a7 dq2 a8 dq3 a9 dq4 a10 dq5 a11 dq6 a12 dq7 a13 a14 e\ g\ & 10 [pwr dwn] 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 en a a a a a a a a 11 12 13 15 16 17 18 19 eprom 32,768 x 8 0 14 a 0 32,767 read output disable standby programming verify program inhibit e\ (20) v il v il v ih v il v ih v ih g\ (22) v il v ih x v ih v il x v pp (1) v cc v cc v cc v pp v pp v pp v cc (28) v cc v cc v cc v cc v cc v cc a9 (24) x x x x x x v id v id a0 (10) x x x x x x v il v ih mfg device 97 v cc function (pins) signature mode mode* dq0-dq7 (11-13, 15-19) v cc v il v il data out high-z high-z data in data out high-z code 04
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 read/output disable when the outputs of two or more smj27c256s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. to read the output of the selected smj27c256, a low-level signal is applied to e\ and g\. all other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. output data is accessed at pins dq0 through dq7. latchup immunity latchup immunity on the smj27c256 is a minimum of 250ma on all inputs and outputs. this feature provides latchup immunity beyond any potential transients at the printed circuit board level when the eprom is interfaced to industry standard ttl or mos logic devices. input/output layout approach controls latchup without compromising performance or packing density. power down active i cc supply current can be reduced from 25ma (smj27c256-15 through smj27c256-25) to 500a (ttl- level inputs) or 300a (cmos-level inputs) by applying a high ttl/cmos signal to the e\ pin. in this mode all outputs are in the high-impedance state. erasure before programming, the smj27c256 is erased by exposing the chip through the transparent lid to a high-intensity ultra- violet light (wavelength 2537 ?). eprom erasure before programming is necessary to ensure that all bits are in the logic-high state. logic-lows are programmed into the desired locations. a programmed logic-low can be erased only by ultraviolet light. the recommended minimum exposure dose (uv intensity x exposure time) is 15w?s/cm 2 . a typical 12mw/cm 2 , filterless uv lamp erases the device in 21 minutes. the lamp should be located about 2.5cm above the chip during erasure. after erasure, all bits are in the high state. it should be noted that normal ambient light contains the correct wavelength for erasure; therefore, when using the smj27c256, the window should be covered with an opaque label. snap! pulse programming the smj27c256 eprom is programmed by using the snap! pulse programming algorithm as illustrated by the flowchart in figure 1. this algorithm programs the device in a nominal time of 4 seconds. actual programming time varies as a function of the programmer used. data is presented in parallel (eight bits) on pins dq0 to dq7. once addresses and data are stable, e\ is pulsed. the snap! pulse programming algorithm uses initial pulses of 100 microseconds (s) followed by a byte-verification step to determine when the addressed byte has been successfully programmed. up to ten 100s pulses per byte are provided before a failure is recognized. the programming mode is achieved when v pp = 13v, v cc = 6.5v, g\ = v ih , and e\ = v il . more than one device can be programmed when the devices are connected in parallel. locations can be programmed in any order. when the snap! pulse programming routine is completed, all bits are verified with v cc = v pp = 5v. program inhibit programming can be inhibited by maintaining a high-level input on e\. program verify programmed bits can be verified with v pp = 13v when g\ = v il , and e\ = v ih . signature mode the signature mode provides access to a binary code identifying the manufacturer and device type. this mode is activated when a9 is forced to 12v 0.5v. two identifier bytes are accessed by a0 (terminal 10); i.e., a0=v il accesses the manufacturer code, which is output on dq0-dq7; a0=v ih accesses the device code, which is also output on dq0-dq7. all other addresses must be held at vil. each byte contains odd parity on bit dq7. the manufacturer code for these devices is 97h and the device code is 04h.
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 figure 1. snap! pulse programming flow chart start address = first location increment address x = 0 last address? v cc = v pp = 5v 10% compare all bytes to original data device passed increment address address = first location v cc = 6.5v, v pp = 13v program one pulse = t w = 100s last address? x = x+1 x = 10? program one pulse = t w(e)pr = 100s no fail no yes verify byte no pass device failed yes yes pass fail program mode interactive mode final verification
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** all voltage values are with respect to gnd. absolute maximum ratings* supply voltage range, v cc **...........................-0.6v to +7.0v supply voltage range, v pp **.........................-0.6v to +14.0v input voltage range, all inputs except a9 ** ..-0.6v to +6.5v a9.....-0.6v to +13.5v output voltage range**...............................-0.6v to v cc +1v minimum operating free-air temperature, t a ..............-55c maximum operating case temperature, t c ...................125c storage temperature range, t stg .....................-65c to 150c recommended operating conditions notes: 1. v cc must be applied before or at the same time as v pp and removed after or at the same time as v pp . the deivce must not be inserted into or removed from the board when v pp or v cc is applied. 2. v pp can be connected to v cc directly (except in the program mode). v cc supply current in this case would be i cc2 + i pp1 . electrical characteristics over recommended ranges of supply voltage and operating free-air temperature notes: 1. typical values are at t a =25c and nominal voltages. 2. this parameter has been characterized at 25c and is not tested. min typ max unit 4.5 5 5.5 v 6.25 6.5 6.75 v v cc -0.6 v 12.75 13 13.25 v ttl inputs 2 v cc +1 v cmos inputs v cc -0.2 v cc +1 v ttl inputs -0.5 0.8 v cmos inputs -0.5 0.2 v v id 11.5 13 v t a -55 c t c +125 c v cc read mode 1 snap! pulse programming algorithm supply voltage read mode 2 snap! pulse programming algorithm v pp high-level input voltage v ih supply voltage v il low-level input voltage operating free-air temperature operating case temperature voltage level on a9 for signature mode test conditions min typ 1 max unit v oh i oh = -400a 2.4 v v ol i ol = 2.1ma 0.4 v i i v i = 0v to 5.5v 1 a i o v o = 0v to v cc 1 a i pp1 v pp = v cc = 5.5v 10 a i pp2 v pp = 13v 35 50 ma ttl-input level v cc = 5.5v, e\=v ih 500 a cmos-input level v cc = 5.5v, e\=v cc 300 a i cc2 v cc supply current (active) '27c256-15 '27c256-17 '27c256-20 '27c256-25 e\=v il , v cc =5.5v t cycle = minimum, outputs open 15 25 ma i os 100 ma output current (leakage) parameter i cc1 v cc supply current (standby) high-level output voltage low-level output voltage input current (leakage) v pp supply current output current (leakage) v pp supply current (during program pulse) 2
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1mhz* * capacitance measurements are made on a sample basis only. ** typical values are at t a = 25c and nominal voltages. switching characteristics over recommended ranges of supply voltage and operating free-air temperature 1,2 notes: 1.timing measurements are made at 2v for logic high and 0.8v for logic low (see figure 2). 2. common test conditions apply for t dis except during programming. 3. value calculated from 0.5v delta to measured output level. this parameter is only sampled and not 100% tested. test conditions typ** max unit c i input capacitance v i = 0v 610pf c o output capacitance v o = 0v 10 14 pf parameter min max min max t a(a) access time from address 150 170 ns t a(e) access time from e\ 150 170 ns t en(g)r output enable time from g\ 70 70 ns t dis disable time of output from g\ or e\, whichever occurs first 3 055055 ns t v(a) output data valid time after change of address, e\, or g\, whichever occurs first 3 00 ns parameter -15 see figure 2 -17 unit test conditions 1, 2 min max min max min max t a(a) access time from address 200 250 300 ns t a(e) access time from e\ 200 250 300 ns t en(g)r output enable time from g\ 75 100 120 ns t dis disable time of output from g\ or e\, whichever occurs first 3 0 60 0 60 0 105 ns t v(a) output data valid time after change of address, e\, or g\, whichever occurs first 3 000 ns parameter -20 -25 see figure 2 -30 unit test conditions 1, 2 switching characteristics for programming: v cc = 6.5v and v pp = 13v (snap! pulse), t a = 25c min max unit t dis(g) output disable time from g\ 0 130 ns t en(g)w output enable time from g\ 150 ns parameter
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 recommended timing requirements for programming: v cc = 6.5 and v pp = 13 (snap! pulse), t a = 25c (see figure 2) min typ max unit t h(a) 0s t h(d) 2s t w(e)pr 95 100 105 s t su(a) 2s t su(g) 2s t su(e) 2s t su(d) 2s t su(vpp) 2s t su(vcc) 2s hold time, address hold time, data setup time, address pulse duration, initial program setup time, v cc setup time, g\ setup time, e\ setup time, data setup time, v pp parameter measurement information notes: 1. c l includes probe and fixture capacitance. 2.08v output under test r l = 800 w cl = 100 pf 1 figure 2. load circuit and voltage waveforms the ac testing inputs are driven at 2.4v for logic high and 0.4v for logic low. timing measurements are made at 2v for logic high and 0.8v for logic low for both inputs and outputs.
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 figure 3. read-cycle timing figure 4. program-cycle timing (snap! pulse programming)
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 mechanical definition* note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. *all measurements are in inches. asi case #110 (package designator cw) smd 5962-86063, case outline x s2 a q l e b b2 s1 min max a --- 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d --- 1.490 e 0.500 0.610 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 --- s2 0.005 --- symbol 0.100 bsc smd specifications 0.600 bsc ea c d e
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 *available processes m = extended temperature range -55 o c to +125 o c ordering information device number speed ns package type operating temp. smj27c256 -15 j * smj27c256 -17 j * smj27c256 -20 j * smj27c256 -25 j * smj27c256 -30 j * example: smj27c256-30jm
uveprom smj27c256 austin semiconductor, inc. smj27c256 rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 asi to dscc part number cross reference* asi package designator j ti p ar t #** smd p ar t # smj27c256-15jm 5962-8606305xa SMJ27C256-17JM 5962-8606304xa smj27c256-20jm 5962-8606301xa smj27c256-25jm 5962-8606302xa smj27c256-30jm 5962-8606303xa * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd. ** parts are listed on smd under the old texas instruments part number. asi purchased this product line in november of 1999.

▲Up To Search▲

Price & Availability of SMJ27C256-17JM

	To Download SMJ27C256-17JM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .